Burn-in operations are often performed on semiconductor devices to exercise and stress those circuits that may fail early in the product's life cycle. Conventional burn-in processes for devices that include memory arrays write data to each memory cell in the memory array. This is done using a socket that includes pins that electrically connect to each data input terminal of the memory array, and pins that electrically connect with other terminals required for the burn-in (e.g., power, ground, etc). This is a parallel process, with data transmitted in parallel to each data input terminal of each device under test.
The types of inexpensive sockets typically used in burn-in testing have been adequate in the past as there has not been a need to connect to a large number of pins on the packaged semiconductor device. However, the size of memory arrays keeps increasing, resulting in the need to connect to more and more input data terminals of each memory array. In order to assure good contact with all of the pins of the device under test more expensive sockets must be used, resulting in increased cost. Moreover, as the pin-count increases, reliability decreases and the time required to perform each burn-in increases. Also, the number of required connections is limited by the capabilities of the card-edge connector on the burn-in board that is used to connect to the burn-in driver. With the high number of pin counts of recent semiconductor devices this will result in the need to buy new connectors and/or the need to reduce the number of sockets on a particular burn-in board.
Most semiconductor devices that include memory arrays are now compliant with the Joint Test Action Group (JTAG) standard, formally known as IEEE/ANSI Standard 1149.1. This standard was originally developed as an on-chip test infrastructure to extend the lifetime of available automatic test equipment. Semiconductor devices that conform to the JTAG standard include a boundary scan cell that is connected to each input, output or bi-directional terminal. The JTAG circuitry is transparent during normal operation of the chip such that it does not interfere with normal operation of the chip. However, when the device is placed in the test mode, input signals can be captured for later analysis and output signals can be set to affect other devices on the board.
Accordingly, what is needed is a method and apparatus that will allow for burn-in of semiconductor devices having memory arrays. Also, a method and apparatus is needed that will allow for burn-in of JTAG-compliant devices. In addition, a method and apparatus is needed that will meet the above needs and that is less expensive and more reliable.